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general description the max5054?ax5057 dual, high-speed mosfet drivers source and sink up to 4a peak current. these devices feature a fast 20ns propagation delay and 20ns rise and fall times while driving a 5000pf capacitive load. propagation delay time is minimized and matched between the inverting and noninverting inputs and between channels. high sourcing/sinking peak cur- rents, low propagation delay, and thermally enhanced packages make the max5054?ax5057 ideal for high- frequency and high-power circuits. the max5054?ax5057 operate from a 4v to 15v single power supply and consume 40? (typ) of supply current when not switching. these devices have internal logic circuitry that prevents shoot-through during output state changes to minimize the operating current at high switching frequency. the logic inputs are protected against voltage spikes up to +18v, regardless of the v dd voltage. the max5054a is the only version that has cmos input logic levels while the max5054b/max5055/ max5056/max5057 have ttl input logic levels. the max5055?ax5057 provide the combination of dual inverting, dual noninverting, and inverting/noninverting input drivers. the max5054 feature both inverting and noninverting inputs per driver for greater flexibility. they are available in 8-pin tdfn (3mm x 3mm), standard so, and thermally enhanced so packages. these devices operate over the automotive temperature range of -40? to +125?. applications power mosfet switching motor control switch-mode power supplies power-supply modules dc-dc converters features 4v to 15v single power supply 4a peak source/sink drive current 20ns (typ) propagation delay matching delay between inverting and noninverting inputs matching propagation delay between two channels v dd / 2 cmos logic inputs (max5054aata) ttl logic inputs (max5054b/max5055/max5056/max5057) 0.1 x v dd (cmos) and 0.3v (ttl) logic-input hysteresis up to +18v logic inputs (regardless of v dd voltage) low input capacitance: 2.5pf (typ) 40 a (typ) quiescent current -40c to +125c operating temperature range 8-pin tdfn and so packages max5054?ax5057 4a, 20ns, dual mosfet drivers ________________________________________________________________ maxim integrated products 1 ordering information max5054 ina+ ina- inb+ inb- outb outa v dd gnd pwm in v out v in typical operating circuit 19-3348; rev 3; 3/11 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. * ep = exposed pad. /v denotes an automotive qualified part. + denotes a lead(pb)-free/rohs-compliant package. part temp range pin- package top mark max5054 aata+ -40 c to +125 c 8 tdfn-ep* ags max5054aata/v+ -40 c to +125 c 8 tdfn-ep* bmf max5054bata+ -40 c to +125 c 8 tdfn-ep* agr max5055 aasa+ -40 c to +125 c 8 so-ep* max5055basa+ -40 c to +125 c 8 so max5056 aasa+ -40 c to +125 c 8 so-ep* max5056basa+ -40 c to +125 c 8 so max5057 aasa+ -40 c to +125 c 8 so-ep* max5057basa+ -40 c to +125 c 8 so selector guide and pin configurations appear at end of data sheet.
4a, 20ns, dual mosfet drivers 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = 4v to 15v, t a = -40? to +125?, unless otherwise noted. typical values are at v dd = 15v and t a = +25 c.) (note 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (voltages referenced to gnd.) v dd ...............................................................................-0.3v to +18v ina+, ina-, inb+, inb- ...............................................-0.3v to +18v outa, outb...................................................-0.3v to (v dd + 0.3v) outa, outb short-circuit duration ........................................10ms continuous source/sink current at out_ (p d < p dmax ) .....200ma continuous power dissipation (t a = +70?) 8-pin tdfn-ep (derate 18.2mw/? above +70?)........1454mw 8-pin so-ep (derate 19.2mw/? above +70?) ........1538mw 8-pin so (derate 5.9mw/? above +70?) ..................471mw operating temperature range..............................-40? to +125? storage temperature range .................................-65? to +150? junction temperature ...........................................................+150? lead temperature (soldering, 10s)......................................+300? soldering temperature (reflow) ............................................+260? package thermal characteristics (note 1) max5054?ax5057 parameter symbol conditions min typ max units power supply v dd operating range v dd 415v v dd undervoltage lockout uvlo v dd rising 3.00 3.50 3.85 v v dd undervoltage lockout hysteresis 200 mv v dd undervoltage lockout to output delay v dd rising 12 ? v dd = 4v 28 55 i dd ina- = inb- = v dd , ina+ = inb+ = 0v (not switching) v dd = 15v 40 75 ? v dd supply current i dd-sw ina- = 0v, inb+ = v dd = 15v, ina+ = inb- both channels switching at 250khz, c l = 0f 1 2.4 4 ma driver output (sink) t a = +25? 1.1 1.8 v dd = 15v, i out_ = -100ma t a = +125? 1.5 2.4 t a = +25? 2.2 3.3 driver output resistance pulling down r on-n v dd = 4.5v, i out_ = -100ma t a = +125? 3.0 4.5 ? peak output current (sinking) i pk-n v dd = 15v, c l = 10,000pf 4 a v dd = 4.5v 0.45 output-voltage low i out_ = -100ma v dd = 15v 0.24 v latchup protection i lup reverse current i out_ (note 2) 400 ma 8 tdfn-ep junction-to-ambient thermal resistance ( ja )...............+41?/w junction-to-case thermal resistance ( jc )......................+8?/w 8 so junction-to-ambient thermal resistance ( ja )................+132?/w junction-to-case thermal resistance ( jc ).......................+40?/w 8 so-ep junction-to-ambient thermal resistance ( ja )..................+41?/w junction-to-case thermal resistance ( jc )......................+7?/w note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial .
max5054?ax5057 4a, 20ns, dual mosfet drivers _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = 4v to 15v, t a = -40? to +125?, unless otherwise noted. typical values are at v dd = 15v and t a = +25 c.) (note 2) parameter symbol conditions min typ max units driver output (source) t a = +25? 1.5 2.1 v dd = 15v, i out_ = 100ma t a = +125? 1.9 2.75 t a = +25? 2.75 4 driver output resistance pulling up r on-p v dd = 4.5v, i out_ = 100ma t a = +125? 3.75 5.5 ? peak output current (sourcing) i pk-p v dd = 15v, c l = 10,000pf 4 a v dd = 4.5v v dd - 0.55 output-voltage high i out_ = 100ma v dd = 15v v dd - 0.275 v logic input (note 4) max5054a 0.7 x v dd logic 1 input voltage v ih max5054b/max5055/max5056/max5057 (note 5) 2.1 v max5054a 0.3 x v dd logic 0 input voltage v il max5054b/max5055/max5056/max5057 0.8 v max5054a 0.1 x v dd logic-input hysteresis v hys max5054b/max5055/max5056/max5057 0.3 v logic-input-current leakage ina+, inb+, ina-, inb- = 0v or v dd -1 +0.1 +1 a input capacitance c in 2.5 pf switching characteristics for v dd = 15v (figure 1) c l = 1000pf 4 c l = 5000pf 18 out_ rise time t r c l = 10,000pf 32 ns c l = 1000pf 4 c l = 5000pf 15 out_ fall time t f c l = 10,000pf 26 ns turn-on delay time t d-on c l = 10,000pf (note 3) 10 20 34 ns turn-off delay time t d-off c l = 10,000pf (note 3) 10 20 34 ns switching characteristics for v dd = 4.5v (figure 1) c l = 1000pf 7 c l = 5000pf 37 out_ rise time t r c l = 10,000pf 85 ns c l = 1000pf 7 c l = 5000pf 30 out_ fall time t f c l = 10,000pf 75 ns turn-on delay time t d-on c l = 10,000pf (note 3) 18 35 70 ns turn-off delay time t d-off c l = 10,000pf (note 3) 18 35 70 ns
max5054?ax5057 4a, 20ns, dual mosfet drivers 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = 4v to 15v, t a = -40? to +125?, unless otherwise noted. typical values are at v dd = 15v and t a = +25 c.) (note 1) parameter symbol conditions min typ max units matching characteristics v dd = 15v, c l = 10,000pf 2 mismatch propagation delays from inverting and noninverting inputs to output ? t on-off v dd = 4.5v, c l = 10,000pf 4 ns v dd = 15v, c l = 10,000pf 1 mismatch propagation delays between channel a and channel b ? t a-b v dd = 4.5v, c l = 10,000pf 2 ns note 2: all devices are 100% tested at t a = +25?. specifications over -40? to +125? are guaranteed by design. note 3: limits are guaranteed by design, not production tested. note 4: the logic-input thresholds are tested at v dd = 4v and v dd = 15v. note 5: ttl compatible with reduced noise immunity. rise time vs. supply voltage (c l = 5000pf) max5054 toc01 supply voltage (v) rise time (ns) 14 12 10 8 6 10 20 30 40 50 60 0 416 t a = +125 c t a = +25 c t a = -40 c fall time vs. supply voltage (c l = 5000pf) max5054 toc02 t a = +125 c t a = +25 c t a = -40 c fall time (ns) 10 20 30 40 50 60 0 supply voltage (v) 14 12 10 8 6 416 propagation delay time, low-to-high vs. supply voltage (c l = 5000pf) max5054 toc03 t a = +125 c t a = +25 c t a = -40 c propagation delay (ns) 10 20 30 40 50 60 0 supply voltage (v) 14 12 10 8 6 416 max5054 toc04 propagation delay time, high-to-low vs. supply voltage (c l = 5000pf) t a = +125 c t a = +25 c t a = -40 c propagation delay (ns) 10 20 30 40 50 60 0 supply voltage (v) 14 12 10 8 6 416 i dd-sw supply current vs. supply voltage max5054 toc05 supply voltage (v) i dd-sw supply current (ma) 14 12 10 8 6 1 2 3 4 5 6 0 416 duty cycle = 50% v dd = 15v, c l = 0 1 channel switching 1mhz 50khz 100khz 500khz supply current vs. supply voltage max5054 toc06 supply voltage (v) supply current (ma) 14 12 10 8 6 10 20 30 40 50 60 70 80 90 100 0 416 duty cycle = 50% v dd = 15v, c l = 4700pf 1 channel switching 1mhz 50khz 100khz 500khz typical operating characteristics (t a = +25?, unless otherwise noted.)
max5054?ax5057 4a, 20ns, dual mosfet drivers _______________________________________________________________________________________ 5 max5054 toc07 temperature ( c) supply current (ma) 100 75 50 25 0 -25 1.5 2.0 2.5 3.0 3.5 4.0 1.0 -50 125 i dd-sw supply current vs. temperature v dd = 15v, f = 250khz, c l = 0 duty cycle = 50% both channels switching input threshold voltage vs. supply voltage max5054 toc08 supply voltage (v) input threshold voltage (v) 14 12 10 8 6 1 2 3 4 5 6 7 8 9 10 0 416 max5054aata (cmos input) v in rising v in falling max5054 toc09 supply voltage (v) input threshold voltage (v) 14 12 10 8 6 0.5 1.0 1.5 2.0 2.5 3.0 0 416 input threshold voltage vs. supply voltage v in rising v in falling ttl input versions supply current vs. logic-input voltage (input low-to-high) max5054 toc10 logic-input voltage (v) supply current ( a) 14 12 10 8 6 4 2 100 200 300 400 500 0 016 ttl input versions v dd = 15v max5054 toc11 logic-input voltage (v) supply current ( a) 14 12 10 8 6 4 2 100 200 300 400 500 0 016 supply current vs. logic-input voltage (input high-to-low) ttl input versions v dd = 15v max5054 toc12 logic-input voltage (v) supply current (ma) 14 12 10 8 6 4 2 1 2 3 4 5 0 016 supply current vs. logic-input voltage (input low-to-high) max5054aata (cmos input) v dd = 15v max5054 toc13 logic-input voltage (v) supply current (ma) 14 12 10 8 6 4 2 1 2 3 4 5 0 016 supply current vs. logic-input voltage (input high-to-low) max5054aata (cmos input) v dd = +15v delay mismatch between in_+ and in_- to out_ vs. temperature max5054 toc14 temperature ( c) delay mismatch (ns) 100 75 50 25 0 -25 -4 -2 0 2 4 6 -6 -50 125 output falling output rising max5054aata (cmos input) v dd = 4.5v, c l = 10,000pf max5054 toc15 temperature ( c) delay mismatch (ns) 100 75 50 25 0 -25 -4 -2 0 2 4 6 -6 -50 125 delay mismatch between in_+ and in_- to out_ vs. temperature output falling output rising max5054aata (cmos input) v dd = 15v, c l = 10,000pf typical operating characteristics (continued) (t a = +25?, unless otherwise noted.)
max5054?ax5057 4a, 20ns, dual mosfet drivers 6 _______________________________________________________________________________________ typical operating characteristics (continued) (t a = +25?, unless otherwise noted.) max5054 toc16 temperature ( c) delay mismatch (ns) 100 75 -25 0 25 50 -3 -2 -1 0 1 2 3 4 -4 -50 125 delay mismatch between 2 channels vs. temperature v dd = 4.5v, c l = 10,000pf output rising output falling max5054 toc17 temperature ( c) delay mismatch (ns) 100 75 -25 0 25 50 -3 -2 -1 0 1 2 3 4 -4 -50 125 delay mismatch between 2 channels vs. temperature v dd = 15v, c l = 10,000pf output rising output falling logic-input voltage vs. output voltage (v dd = 4v, c l = 5000pf) max5054 toc18 in_- 2v/div 20ns/div out_ 2v/div max5055 (ttl input) max5054 toc19 40ns/div logic-input voltage vs. output voltage (v dd = 4v, c l = 10,000pf) in_- 2v/div out_ 2v/div max5055 (ttl input) max5054 toc20 20ns/div logic-input voltage vs. output voltage (v dd = 4v, c l = 5000pf) in_- 2v/div out_ 2v/div max5055 (ttl input) max5054 toc21 40ns/div logic-input voltage vs. output voltage (v dd = 4v, c l = 10,000pf) in_- 2v/div out_ 2v/div max5055 (ttl input)
max5054?ax5057 4a, 20ns, dual mosfet drivers _______________________________________________________________________________________ 7 max5054 toc22 20ns/div logic-input voltage vs. output voltage (v dd = 15v, c l = 5000pf) in_- 2v/div out_ 5v/div max5055 max5054 toc23 40ns/div logic-input voltage vs. output voltage (v dd = 15v, c l = 10,000pf) in_- 2v/div out_ 5v/div max5055 max5054 toc24 20ns/div logic-input voltage vs. output voltage (v dd = 15v, c l = 5000pf) in_- 2v/div out_ 5v/div max5055 max5054 toc25 40ns/div logic-input voltage vs. output voltage (v dd = 15v, c l = 10,000pf) max5055 in_- 2v/div out_ 5v/div v dd vs. output voltage max5054 toc26 2ms/div max5055 ina- = inb- = gnd c la = c lb = 10,000pf v dd 5v/div outb 5v/div outa 5v/div max5054 toc27 2ms/div v dd vs. output voltage max5055 ina- = inb- = gnd c la = c lb = 10,000pf v dd 5v/div outb 5v/div outa 5v/div typical operating characteristics (continued) (t a = +25?, unless otherwise noted.)
max5054?ax5057 4a, 20ns, dual mosfet drivers 8 _______________________________________________________________________________________ pin descriptions pin name function 1 ina- inverting logic-input terminal for driver a. connect to gnd when not used. 2 inb- inverting logic-input terminal for driver b. connect to gnd when not used. 3 gnd ground 4 outb driver b output. sources or sinks current for channel b to turn the external mosfet on or off. 5v dd power supply. bypass to gnd with one or more 0.1? ceramic capacitors. 6 outa driver a output. sources or sinks current for channel a to turn the external mosfet on or off. 7 inb+ noninverting logic-input terminal for driver b. connect to v dd when not used. 8 ina+ noninverting logic-input terminal for driver a. connect to v dd when not used. ?p exposed pad. internally connected to gnd. do not use the exposed pad as the only electrical ground connection. pin max5055 max5056 max5057 name function 1, 8 1, 8 1, 8 n.c. no connection. not internally connected. 2 2 ina- inverting logic-input terminal for driver a. connect to gnd if not used. 3 3 3 gnd ground 4 inb- inverting logic-input terminal for driver b. connect to gnd if not used. 5 5 5 outb driver b output. sources or sinks current for channel b to turn the external mosfet on or off. 666v dd power supply. bypass to gnd with one or more 0.1? ceramic capacitors. 7 7 7 outa driver a output. sources or sinks current for channel a to turn the external mosfet on or off. 4 4 inb+ noninverting logic-input terminal for driver b. connect to v dd if not used. 2 ina+ noninverting logic-input terminal for driver a. connect to v dd if not used. ep exposed pad. internally connected to gnd. do not use the exposed pad as the only electrical ground connection. max5054 max5055/max5056/max5057
detailed description v dd undervoltage lockout (uvlo) the max5054?ax5057 have internal undervoltage lockout for v dd . when v dd is below the uvlo thresh- old, out_ is low, independent of the state of the inputs. the undervoltage lockout is typically 3.5v with 200mv typical hysteresis to avoid chattering. when v dd rises above the uvlo threshold, the outputs go high or low depending upon the logic-input levels. bypass v dd using low-esr ceramic capacitors for proper operation (see the applications information section). logic inputs the max5054b?ax5057 have ttl-compatible logic inputs, while the max5054a is a cmos logic-input dri- ver. the logic-input signals can be independent of the v dd voltage. for example, the device can be powered by a 5v supply while the logic inputs are provided from cmos logic. also, the logic inputs are protected against the voltage spikes up to 18v, regardless of the v dd volt- age. the ttl and cmos logic inputs have 300mv and 0.1 x v dd hysteresis, respectively, to avoid possible dou- ble pulsing during transition. the low 2.5pf input capaci- tance reduces loading and increases switching speed. max5054?ax5057 4a, 20ns, dual mosfet drivers _______________________________________________________________________________________ 9 v ih v il 90% 10% v ih v il t r t f t d-off1 t d-on1 t d-off2 t d-on2 in_+ out_ in_- rising mismatch = t d-on2 - t d-on1 falling mismatch = t d-off2 - t d-off1 figure 1. timing diagram p n max5054 break- before- make control v dd out_ gnd in_- in_+ figure 2. max5054 block diagram (1 driver) p n max5055 max5056 max5057 break- before- make control v dd out_ gnd in_+ noninverting input driver p n max5055 max5056 max5057 break- before- make control v dd out_ gnd in_- inverting input driver figure 3. max5055/max5056/max5057 functional diagrams (1 driver)
max5054?ax5057 the logic inputs are high impedance and must not be left floating. if the inputs are left open, out_ can go to an undefined state as soon as v dd rises above the uvlo threshold. therefore, the pwm output from the controller must assume proper state when powering up the device. the max5054 has two logic inputs per driver providing greater flexibility in controlling the mosfet. use in_+ for noninverting logic and in_- for inverting logic operation. connect in_+ to v dd and in_- to gnd if not used. alternatively, the unused input can be used as an on/off function. use in_+ for active-low shutdown logic and in_- for active-high shutdown logic (see figure 4). see table 1 for all possible input combinations. driver output the max5054?ax5057 have low r ds(on) p-channel and n-channel devices (totem pole) in the output stage for the fast turn-on and turn-off high gate-charge switch- ing mosfets. the peak source or sink current is typically 4a. the out_ voltage is approximately equal to v dd when in high state and is ground when in low state. the driver r ds(on) is lower at higher v dd , thus higher source-/sink-current capability and faster switching speeds. the propagation delays from the noninverting and inverting logic inputs to outputs are matched to 2ns. the break-before-make logic avoids any cross-conduc- tion between the internal p- and n-channel devices, and eliminates shoot-through currents reducing the quiescent supply current. applications information rlc series circuit the driver? r ds(on) (r on ), internal bond and lead inductance (l p ), trace inductance (l s ), gate inductance (l g ), and gate capacitance (c g ) form a series rlc circuit with a second-order characteristic equation. the series rlc circuit has an undamped natural frequency ( ? 0 ) and a damping ratio ( ) where: the damping ratio needs to be greater than 0.5 (ideally 1) to avoid ringing. add a small resistor (r gate ) in series with the gate when driving a very low gate-charge mosfet, or when the driver is placed away from the mosfet. use the following equation to calculate the series resistor: l p can be approximated as 3nh and 2nh for so and tdfn packages, respectively. l s is on the order of 20nh/in. verify l g with the mosfet vendor. r lll c r gate psg g on ++ ? () ? 0 1 2 = ++ = ++ () () lll c r lll c psg g on psg g 4a, 20ns, dual mosfet drivers 10 ______________________________________________________________________________________ max5054a v dd gnd ina- ina+ outa pwm input on off figure 4. unused input as an on/off function (1/2 max5054a) table 1. max5054 truth table ina+/inb+ ina-/inb- outa/outb low low low low high low high low high high high low table 2. max5055/max5056/max5057 truth table noninverting in_+ out_ low low high high inverting in_- out_ low high high low
supply bypassing and grounding pay extra attention to bypassing and grounding the max5054?ax5057. peak supply and output currents may exceed 8a when both drivers drive large external capacitive loads in phase. supply voltage drops and ground shifts create forms of negative feedback for inverters and may degrade the delay and transition times. ground shifts due to insufficient device grounding may also disturb other circuits sharing the same ac ground return path. any series inductance in the v dd , out_, and/or gnd paths can cause oscillations due to the very high di/dt when switching the max5054?ax5057 with any capacitive load. place one or more 0.1? ceramic capacitors in parallel as close to the device as possible to bypass v dd to gnd. use a ground plane to minimize ground return resistance and series inductance. place the external mosfet as close as possible to the max5054?ax5057 to further minimize board induc- tance and ac path impedance. power dissipation power dissipation of the max5054?ax5057 consists of three components: caused by the quiescent current, capacitive charge/discharge of internal nodes, and the output current (either capacitive or resistive load). maintain the sum of these components below the maxi- mum power dissipation limit. the current required to charge and discharge the internal nodes is frequency dependent (see the supply current vs. supply voltage graph in the typical operating characteristics ). the power dissipation (p q ) due to the quiescent switching supply current (i dd-sw ) per driver can be calculated as: p q = v dd x i dd-sw for capacitive loads, use the following equation to esti- mate the power dissipation per driver: p cload = c load x (v dd ) 2 x f sw where c load is the capacitive load, v dd is the supply voltage, and f sw is the switching frequency. calculate the total power dissipation (p t ) per driver as follows: p t = p q + p cload use the following equation to estimate the max5054 max5057 total power dissipation per driver when driving a ground-referenced resistive load: p t = p q + p rload p rload = d x r on(max) x i load 2 where d (duty cycle) is the fraction of the period the max5054?ax5057? output pulls high duty cycle, r on(max) is the maximum on-resistance of the device with the output high, and i load is the output load current of the max5054?ax5057. layout information the max5054?ax5057 mosfet drivers source and sink large currents to create very fast rising and falling edges at the gate of the switching mosfet. the high di/dt can cause unacceptable ringing if the trace lengths and impedances are not well controlled. use the following pc board layout guidelines when designing with the max5054?ax5057: place one or more 0.1? decoupling ceramic capacitors from v dd to gnd as close to the device as possible. connect v dd and gnd to large copper areas. place one bulk capacitor of 10? (min) on the pc board with a low resistance path to the v dd input and gnd of the max5054?ax5057. two ac current loops form between the device and the gate of the driven mosfet. the mosfet looks like a large capacitance from gate to source when the gate pulls low. the active current loop is from the mosfet gate to out_ of the max5054?ax5057, to gnd of the max5054?ax5057, and to the source of the mosfet. when the gate of the mosfet pulls high, the active current is from the v dd terminal of the decoupling capacitor, to v dd of the max5054 max5057, to out_ of the max5054?ax5057, to the mosfet gate, to the mosfet source, and to the negative terminal of the decoupling capacitor. both charging current and discharging current loops are important. minimize the physical distance and the impedance in these ac current paths. keep the device as close to the mosfet as possible. in a multilayer pc board, the inner layers should consist of a gnd plane containing the discharging and charging current loops. pay extra attention to the ground loop and use a low-impedance source when using a ttl logic- input device. fast fall time at out_ may corrupt the input during transition. max5054?ax5057 4a, 20ns, dual mosfet drivers ______________________________________________________________________________________ 11
max5054?ax5057 exposed pad both the so-ep and tdfn-ep packages have an exposed pad on the bottom of their package. these pads are internally connected to gnd. for the best thermal conductivity, solder the exposed pad to the ground plane to dissipate 1.5w and 1.9w in so-ep and tdfn-ep packages, respectively. do not use the ground-connected pads as the only electrical ground connection or ground return. use gnd (pin 3) as the primary electrical ground connection. 4a, 20ns, dual mosfet drivers 12 ______________________________________________________________________________________ additional application circuits max5054 ina+ ina- inb+ inb- outb outa v dd gnd v dd pwm in pwm in max5054 ina+ ina- inb+ inb- outb outa v dd gnd pwm in v out v in figure 5. push-pull converter with synchronous rectification drive using max5054
max5054?ax5057 4a, 20ns, dual mosfet drivers ______________________________________________________________________________________ 13 reg5 r21 24.9k ? 1% c1 100pf 1 rcosc +v in tp1 r25 100k ? c2 390pf 3 rcff 5 css 4 com 6 comp 7 fb 8 reg5 2 syncout c5 4700pf d8 21 r15 31.6k ? 1% r16 10.5k ? 1% c4 4.7 f reg5 reg5 9 reg9 c3 4.7 f reg9 10 pvin c6 0.1 f pvin 11 stt 12 lxvdd 13 lxh c18 1000pf r27 10 ? c19 1 f lxh tp3 14 lxl r3 2.2k ? r11 360 ? c17 0.33 f c24 1000pf 4 3 1 2 u2 r20 0 ? r19 475 ? r12 100k ? 1% c27 0.15 f c36 0.22 f c28 0.047 f r1 11.5k ? 1% r2 2.55k ? 1% v out r23 10 ? trim sense (+) sense (-) r24 10 ? 3 52 1 4 out in pgnd gnd fb u3 reg9 c26 0.1 f c22 2200pf 2kv syncin 28 gnd 24 avin 23 bst 22 drvh 21 xfrmrh 20 uvlo 25 fltint 27 startup on/off 26 r4 1m ? 1% r6 1m ? 1% c7 0.22 f +v in +vin reg9 +v in r5 38.3k ? 1% d1 r7 0 ? r8 8.2 ? 2 c8 4.7 f xfrmrh drvb 19 drvdd 18 pgnd 17 drvl 16 cs 15 ic_paddle drvb reg9 c9 1 f r14 270 ? r9 8.2 ? c20 220pf d3 12 6 5 4 1 2 3 7 8 n2 r17 0.027 ? 1% c21 4.7 f 80v r18 4.7 ? pvin +v in r22 15k ? 1 2 1 6 d5 4t r13 47 ? c34 330pf 2 5 8t d7 1 2 3 2 1 4 5 6 6 7 8 n3 d4 1 2 3 2 1 4 5 7 8 n4 r10 20 ? c23 1000pf 8 10 2t t1 l1 2.4 h u5 5v c31 0.1 f 5 4 3 1 2 v cc out gnd u1: max5051 u2: ps2913-1-m u3: max8515 u4: max5054 u5: max5023m u6: ps9715 n1, n2: si4486 n3, n4: si4864 n5: bss123 an ca u6 lxh r26 560 ? r28 2k ? c13 270 f 4v c14 270 f 4v c15 270 f 4v c33 1 f 10v v out vout sgnd 5v +v in c16 3.3 f 21 d6 c35 1 f c32 1 f 1 2 3 4 8 7 6 5 in out wdi n.c. en gnd reset hold 21 d2 n1 3 2 1 8 7 6 5 4 xfrmrh xfrmrh c10 0.47 f 100v c11 0.47 f 100v c12 1 f 100v c25 0.047 f 100v -v in +v in n5 3 2 1 r29 1 ? xfrmrh drvb max5051 u1 reg5 v out v out max5054 u4 +5v +5v c30 0.1 f 6 4 7 1 ina+ inb- v dd gnd outa outb inb+ ina- 8 2 5 3 29 figure 6. schematic of a 48v input, 3.3v at 15a output synchronously rectified, isolated power supply
max5054?ax5057 4a, 20ns, dual mosfet drivers 14 ______________________________________________________________________________________ chip information process: cmos outa v dd outb 1 2 8 7 ina+ inb+ inb- gnd ina- tdfn-ep top view 3 4 6 5 max5054 v dd outb inb- 1 2 8 7 n.c. outa ina- gnd n.c. so/so-ep 3 4 6 5 max5055 v dd outb inb+ 1 2 8 7 n.c. outa ina+ gnd n.c. so/so-ep 3 4 6 5 max5056 v dd outb inb+ 1 2 8 7 n.c. outa ina- gnd n.c. so/so-ep 3 4 6 5 max5057 pin configurations selector guide part pin- package logic input max5054aata 8 tdfn-ep* v dd / 2 cmos dual inverting and dual noninverting inputs max5054bata 8 tdfn-ep* ttl dual inverting and dual noninverting inputs max5055aasa 8 so-ep* ttl dual inverting inputs max5055basa 8 so ttl dual inverting inputs MAX5056AASA 8 so-ep* ttl dual noninverting inputs max5056basa 8 so ttl dual noninverting inputs max5057aasa 8 so-ep* ttl inverting and noninverting inputs max5057basa 8 so ttl inverting and noninverting inputs * ep = exposed pad. package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package draw- ings may show a different suffix character, but the drawing per- tains to the package regardless of rohs status. package type package code outline no. land pattern no. 8 tdfn-ep t833+2 21-0137 90-0059 8 so-ep s8e+14 21-0111 90-0151 8 so s8+4 21-0041 90-0096
max5054?ax5057 4a, 20ns, dual mosfet drivers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 15 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 8/04 initial release 0 1 9/05 package-related changes tbd 2 9/10 added automotive part; updated package information table 1, 2, 14, 15, 16 3 3/11 corrected top mark discrepancy and actual top mark for max5054aata/v+ 1, 2

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